2016年2月24日星期三

PCB design considerations


不可忽视的电路设计的八个盲点
盲点一:对于设计要求不高的板子用细线自动分布
自动布线必然要占用更大的PCB面积,同时产生比手动布线多好多倍的过孔,在批量很大的产品中,PCB厂家降价所考虑的因素除了商务因素外,就是线宽和过孔数量,它们分别影响到PCB的成品率和钻头的消耗数量,节约了供应商的成本,也就给降价找到了理由。

盲点二:总线信号都用电阻拉一下
信号需要上下拉的原因很多,但也不是个个都要拉。上下拉电阻拉一个单纯的输入信号,电流也就几十微安以下,但拉一个被驱动了的信号,其电流将达毫安级,现在的系统常常是地址数据各32位,可能还有244/245隔离后的总线及其它信号,都上拉的话,几瓦的功耗就耗在这些电阻上了。

盲点三:CPU和FPGA的这些不用的I/O口让它先空着
不用的I/O口如果悬空的话,受外界的一点点干扰就可能成为反复振荡的输入信号了,而MOS器件的功耗基本取决于门电路的翻转次数。如果把它上拉的话,每个引脚也会有微安级的电流,所以最好的办法是设成输出(当然外面不能接其它有驱动的信号)

盲点四:FPGA还剩这么多门用不完,可尽情发挥
FGPA的功耗与被使用的触发器数量及其翻转次数成正比,所以同一型号的FPGA在不同电路不同时刻的功耗可能相差100倍。尽量减少高速翻转的触发器数量是降低FPGA功耗的根本方法。

盲点五:小芯片的功耗都很低不用考虑
对于内部不太复杂的芯片功耗是很难确定的,它主要由引脚上的电流确定,一个ABT16244,没有负载的话耗电大概不到1毫安,但它的指标是每个脚可驱动60毫安的负载(如匹配几十欧姆的电阻),即满负荷的功耗最大可达60*16=960mA,当然只是电源电流这么大,热量都落到负载身上了。

盲点六:存储器多控制信号,板子只需要用OE和WE信号就可以,片选接地,这样读操作时数据出来得快多了
大部分存储器的功耗在片选有效时(不论OE和WE如何)将比片选无效时大100倍以上,所以应尽可能使用CS来控制芯片,并且在满足其它要求的情况下尽可能缩短片选脉冲的宽度。

盲点七:信号过冲只要匹配好就可以消除
除了少数特定信号外(如100BASE-T、CML),都是有过冲的,只要不是很大,并不一定都需要匹配,即使匹配也并非要匹配得最好。象 TTL的输出阻抗不到50欧姆,有的甚至20欧姆,如果也用这么大的匹配电阻的话,那电流就非常大了,功耗是无法接受的,另外信号幅度也将小得不能用,再说一般信号在输出高电平和输出低电平时的输出阻抗并不相同,也没办法做到完全匹配。所以对TTL、LVDS、422等信号的匹配只要做到过冲可以接受即可。

盲点八:降低功耗都是硬件人员的事,与软件没关系
硬件只是搭个舞台,唱戏的却是软件,总线上几乎每一个芯片的访问、每一个信号的翻转差不多都由软件控制的,如果软件能减少外存的访问次数、及时响应中断及其它争对具体单板的特定措施,都将对降低功耗作出很大的贡献。




Baggio WANG FAN
SHENZHEN JAAPSON TECHNOLOGY CO LTD
skype: baggiowang0214
JAAPSON, Expert in HDI Multi-layer PCB Manufacturing

High Frequency PCB Design Techniques

High frequency design is where you really need to consider the effects of parasitic inductance, capacitance and impedance of your PCB layout. If your signal is too fast, and your track is too long, then the track can take on the properties of a transmission line. If you don’t use proper transmission line techniques in these situations then you can start to get reflections and other signal integrity problems.




A “critical length” track is one in which the propagation time of the signal starts to get close to the length of the track. On standard FR4 copper boards, a signal will travel roughly 6 inches every nano second. A rule of thumb states that you need to get really concerned when your track length approaches half of this figure. But in reality it can actually be much less than this. Remember that digital square wave signals have a harmonic content, so a 100MHz square wave can actually have signal components extending into the GHz region.

In high speed design, the ground plane is fundamental to preserving the integrity of your signals, and also reducing EMI emissions. It allows you to create “controlled impedance” traces, which match your electrical source and load. It also allows you to keep signals coupled “tight” to their return path (ground).


There are many ways to create controlled impedance “transmission” lines on a PCB. But the two most basic and popular ways are called Microstrip and Stripline.

A Microstrip is simply a trace on the top layer, with a ground plane below. The calculation involved to find the characteristic impedance of a Microstrip is relatively complex. It is based on the width and thickness of the trace, the height above the ground plane, and the relative permittivity of the PCB material. This is why it is important to keep the ground plane as close as possible to (usually) the top layer.


A Stripline is similar to the Microstrip, but it has an additional ground plane on top of the trace. So in this case, the trace would have to be on one of the inner layers. The advantage of stripline over microstrip is that most of the EMI radiation will be contained within the ground planes.


There are many free programs and spreadsheets available that will calculate all the variations of Microstrip and Stripline for you.

Some useful information and rules of thumb for high frequency design are:
1) Keep your high frequency signal tracks as short as possible.
2) Avoid running critical high frequency signal tracks over any cutout in your ground plane. This causes discontinuity in the signal return path, and can lead to EMI problems. Avoid cutouts in your ground plane wherever possible. A cutout is different to a split plane, which is fine, provided you keep your high frequency signal tracks over the relevant continuous plane.
3) Have one decoupling capacitor per power pin.
4) If possible, track the IC power pin to the bypass capacitor first, and then to the power plane. This will reduce switching noise on your power plane. For very high frequency designs, taking your power pin directly to the power plane provides lower inductance, which may be more beneficial than lower noise on your plane.
5) Be aware that vias will cause discontinuities in the characteristic impedance of a transmission line.
6) To minimize crosstalk between two traces above a ground plane, minimize the distance between the plane and trace, and maximize the distance between traces. The coefficient of coupling between two traces is given by 1/(1+(Distance between traces / height from plane)^2))
7) Smaller diameter vias have lower parasitic inductance, and are thus preferred the higher in frequency you go.

8) Do not connect your main power input connector directly to your power planes, take it via your main filter capacitor(s).




Baggio WANG FAN
SHENZHEN JAAPSON TECHNOLOGY CO LTD
baggio@jaapson-pcb.com  
www.jaapsonpcb.com
skype: baggiowang0214
JAAPSON, Expert in HDI Multi-layer PCB Manufacturing